1. Field of the Invention
The present invention relates to a method and apparatus for driving a plasma display panel (PDP), and more particularly, to a method and apparatus for driving a PDP having a simplified scan electrode driving circuitry.
2. Discussion of the Related Art
FIG. 1 is an internal perspective view showing the structure of a typical surface discharge type triode PDP, and FIG. 2 is a cross-sectional view of a single discharge cell of the PDP shown in FIG. 1.
Referring to FIG. 1 and FIG. 2, address electrode lines AR1, AG1, . . . , AGm, ABm, dielectric layers 11 and 15, Y-electrode lines Y1, . . . , Yn, X-electrode lines X1, . . . , Xn, phosphor layers 16, barrier walls 17, and a protective layer 12, are provided between a front glass substrate 10 and a rear glass substrate 13 of the surface discharge PDP 1.
The address electrode lines AR1, AG1, . . . , AGm, ABm are formed on the front surface of the rear glass substrate 13 in a predetermined pattern. A rear dielectric layer 15 covers the address electrode lines AR1, AG1, . . . , AGm, ABm. The barrier walls 17 are formed on the rear dielectric layer 15 in between, and in parallel to, the address electrode lines AR1, AG1, . . . , AGm, ABm. The barrier walls 17 partition discharge regions of respective discharge cells and prevent cross talk between the discharge cells. The phosphor layers 16 are formed on the rear dielectric layer 15 and on the sides of the barrier walls 17.
The X-electrode lines X1, . . . , Xn and the Y-electrode lines Y1, . . . , Yn are formed in pairs on the rear surface of the front glass substrate 10 to be orthogonal to the address electrode lines AR1, AG1, . . . , AGm, ABm, and their intersections define discharge cells. Each of the X-electrode lines X1, . . . , Xn and the Y-electrode lines Y1, . . . , Yn may include a transparent electrode portion X1a, . . . , Xna and Y1a, . . . , Yna formed of a transparent conductive material, e.g., indium tin oxide (ITO), and a metal electrode portion X1b, . . . , Xnb and Y1b, . . . , Ynb, for increasing conductivity. A front dielectric layer 11 covers the X-electrode lines X1, X2, . . . , Xn and the Y-electrode lines Y1, Y2, . . . , Yn. The protective layer 12, which may be formed of a magnesium oxide (MgO) layer, protects the panel 1 against a strong electrical field, and it is deposited on the front dielectric layer 11. A gas for forming plasma is hermetically sealed in a discharge space 14.
U.S. Pat. No. 5,541,618 discloses an address-display separation (ADS) driving is method for a PDP having the structure shown in FIG. 1.
FIG. 3 is a block diagram of a typical driving apparatus 2 for the PDP 1 of FIG. 1. Referring to FIG. 3, the driving apparatus 2 includes an image processor 26, a logic controller 22, an address driver 23, an X-driver 24, and a Y-driver 25. The image processor 26 converts an external analog image signal into an internal image signal, for example, 8-bit red (R) video data, 8-bit green (G) video data, and 8-bit blue (B) video data, a clock signal, a vertical synchronizing signal, and a horizontal synchronizing signal. The logic controller 22 generates drive controlling signals SA, SY, and SX in response to the internal image signals from the image processor 26.
The address driver 23 processes the address signal SA to generate a display data signal and applies the display data signal to the address electrode lines. The X-driver 24 processes the X-drive controlling signal SX and applies the result to the X-electrode lines. The Y-driver 25 processes the Y-drive controlling signal SY and applies the result to the Y-electrode lines.
FIG. 4 is a timing chart showing an ADS method of driving the PDP 1 of FIG. 1. Referring to FIG. 4, to realize time-division grayscale display, a unit frame may be divided into a plurality of subfields SF1, . . . , SF8. The individual subfields SF1, . . . , SF8 may be further divided into reset periods R1, . . . , R8, address periods A1, . . . , A8, and sustain periods S1, . . . , S8, respectively.
The luminance of the PDP 1 is proportional to a total length of the sustain periods S1, . . . , S8 in a unit frame, which is 255 T (T is a unit of time). A time 2n−1 is set to a sustain period Sn of an nth subfield SFn. Thus, by appropriately selecting a subfield to display, display of 256 grayscales, including grayscale 0, may be performed.
FIG. 5 is a timing chart showing examples of drive signals applied in unit subfields shown in FIG. 4 to electrode lines of the PDP 1 shown in FIG. 1.
In FIG. 5, reference characters SAR1 . . . ABm are drive signals applied to address electrode lines (AR1, AG1, . . . , AGm, ABm of FIG. 1), SX1 . . . Xn are drive signals applied to X-electrode lines (X1, . . . , Xn of FIG. 1), and SY1 . . . Yn are drive signals applied to Y-electrode lines (Y1, . . . , Yn of FIG. 1).
Referring to FIG. 5, a unit subfield SF includes a reset period PR, an address period PA, and a sustain period PS. During the reset period PR, a voltage applied to the X-electrode lines X1, . . . , Xn is raised from a ground voltage VG to a first voltage Ve and simultaneously, a ground voltage VG is applied to the Y-electrode lines Y1, . . . , Yn and the address electrode lines AR1, AG1, . . . , AGm, ABm.
Next, a voltage applied to the Y-electrode lines Y1, . . . , Yn is raised from a second voltage VS (e.g., 155 V) to a maximum voltage (VSET+VS) (e.g., 355 V), and simultaneously, a ground voltage VG is applied to the X-electrode lines X1, . . . , Xn and the address electrode lines AR1, AG1, . . . , AGm, ABm.
Next, while a voltage applied to the X-electrode lines X1, . . . , Xn is maintained at the second voltage VS, a voltage applied to the Y-electrode lines Y1, . . . , Yn reduces from the second voltage VS to the ground voltage VG while simultaneously applying a ground voltage VG to the address electrode lines AR1, AG1, . . . , AGm, ABm.
Thus, during the address period PA, while applying display data signals to the address electrode lines AR1, AG1, . . . , AGm, ABm, a scan signal of the ground voltage VG is sequentially applied to the Y-electrode lines Y1, . . . , Yn, which are biased to a fourth voltage VSCAN, to thereby address the Y-electrode lines Y1, . . . , Yn. Applying display data signals of an address voltage VA to the address electrode lines AR1, AG1, . . . , AGm, ABm selects the respective discharge cell, and a ground voltage VG is applied to an address electrode line when the corresponding discharge cell is not to be selected. Thus, applying an address voltage VA to an address electrode while applying the ground voltage VG to the corresponding Y electroce generates wall charges in corresponding discharge cell due to an address discharge. To facilitate the address discharge, the first voltage Ve may be maintained at the X-electrode lines X1, . . . , Xn during the address period.
During the sustain period PS, a sustain pulse of a second voltage VS is alternately applied to the Y-electrode lines Y1, . . . , Yn and the X-electrode lines X1, . . . , Xn, thereby provoking a display discharge in those discharge cells that were selected during the address period PA.
FIG. 6 is a circuit diagram of a Y-driver of a conventional apparatus for driving a PDP, FIG. 7 is a timing chart showing examples of scan controlling signals applied to a scan drive integrated circuit (IC), and FIG. 8 is a timing chart showing examples of scan controlling signals used in a conventional method of driving a PDP.
Referring to FIG. 6, a Y-driver 25 processes Y drive controlling signals SY to generate a display data signal and applies it to the Y-electrode lines. The Y-driver 25 may include a circuit portion and a scan drive IC 251. The circuit portion applies various voltages (e.g., Vs, Vset, or Vscan) to the Y-electrode lines in the reset period PR, address period PA, and sustain period PS. The scan drive IC 251 enables sequential application of a scan pulse to the Y-electrode lines during the address period PA.
The scan drive IC 251 may include a plurality of output terminals and one scan drive IC may be formed for each Y-electrode line.
The scan drive IC 251 receives scan controlling signals as shown in FIG. 7 and outputs a scan pulse to the Y-electrode lines during the address period. Although the scan controlling signals may be changed depending on the type of the scan drive IC 251, they typically include a clock signal CLK, a data signal Data, a strobe signal STB, a blanking signal BLK, and a high impedance controlling signal HIZ.
The scan drive IC 251 outputs a scan pulse to the Y-electrode lines during the address period PA, and a discharge pulse and a reset pulse may pass through its internal diode path during the sustain period PS and reset period PR. Accordingly, as shown in FIG. 8, the scan drive IC 251 may be grounded at a floating electric potential level, which varies over time, instead of an absolute “0” level. A device for electrically isolating an input controlling signal of the scan drive IC 251 from its output controlling signal may be required to provide such a floating ground.
Conventionally, an optocoupler or a transformer may be used to electrically isolate the scan drive's input signal from the output signal. A typical apparatus for driving a PDP utilizes an optocoupler 252, as shown in FIG. 6. However, when producing PDPs in bulk, providing the optocoupler 252 may increases dispersion of components and defective products, thereby reducing yield.